Date: Tue, 26 Nov 1996 18:51:32 GMT
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    <TITLE>CSE322 Computer Architecture </TITLE>
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<H1>CSE 322: Computer Architecture<BR>
<HR></H1>
<H3>Professor:</H3>
<BLOCKQUOTE><!WA1><A HREF="http://www.cse.nd.edu/~jbb/index.html">Dr. Jay Brockman</A><BR>
384 Fitzpatrick Hall<BR>
phone: 1-8810<BR>
email: <!WA2><A HREF="mailto:%20jbb@cse.nd.edu">jbb@cse.nd.edu</A><BR>
office hours: Tu, Th 2:30-3:30, or by appointment</BLOCKQUOTE>
<H3>Teaching Assistants:</H3>
<BLOCKQUOTE>Lilia Suslov<BR>
email: <!WA3><A HREF="mailto:lsuslov@bach.helios.nd.edu">lsuslov@bach.helios.nd.edu</A><BR>
<BR>
Dave Greene<BR>
email: <!WA4><A HREF="mailto:dgreene1@bach.helios.nd.edu">dgreene1@bach.helios.nd.edu</A><BR>
<BR>
Holly Campbell<BR>
email: <!WA5><A HREF="mailto:hcampbel@bach.helios.nd.edu">hcampbel@bach.helios.nd.edu</A></BLOCKQUOTE>
<H3>Text:</H3>
<BLOCKQUOTE>David A. Patterson and John L. Hennessy. <I>Computer Organization
and Design: The Hardware/Software Interface,</I> Morgan Kaufmann Publishers,
Inc., 1994.</BLOCKQUOTE>
<H3><BR>
Classnotes: </H3>
<UL>
<LI><!WA6><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/Introduction.ps">Introduction</A> 
<LI><!WA7><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/HardwareFirmware.ps">Hardware/Firmware Implementation
of Algorithms</A> 
<LI><!WA8><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/ControlPath.ps">Hardware/Firmware Implementation
of Control</A> 
<LI><!WA9><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/SingleCycle.ps">The Single-Cycle MIPS Processor
</A>
<LI><!WA10><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/MultiCycle.ps">The Multiple Cycle MIPS Processor
</A>
<LI><!WA11><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/Pipeline.ps">Pipelining </A>
<LI><!WA12><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/Hazards.ps">Pipelining Continued: Hazards </A>
<LI><!WA13><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/Cache.ps">Memory Hierarchy </A>
<LI><!WA14><A HREF="http://wizard.cse.nd.edu/class_data/cse322/classnotes/InputOutput.ps">Interfacing Processors, Peripherals,
and Memory </A>
</UL>
<H3>Homework Assignments: </H3>
<UL>
<LI>Homework 1: <!WA15><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework1.ps">Hardware/Firmware Implementation
of Algorithms</A> 
  <UL>
  <LI>Solutions: <!WA16><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw1_1.gif">page 1</A>, <!WA17><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw1_2.gif">page
2</A>, <!WA18><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw1_3.gif">page 3</A> , <!WA19><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw1_4.gif">page
4</A> 
  </UL>
<LI>Homework 2: <!WA20><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework2.ps">Control System Design</A>
  <UL>
  <LI>Solutions: <!WA21><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw2_1.gif">page 1</A>, <!WA22><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw2_2.gif">page
2</A> 
  </UL>
<LI>Homework 3: <!WA23><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework3.ps">Pipelining </A>
  <UL>
  <LI>Solutions: <!WA24><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/pip1_1.gif">page 1</A>, <!WA25><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/pip1_2.gif">page
2</A>, <!WA26><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/pip1_3.gif">page 3</A>, <!WA27><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/pip1_4.gif">page
4</A>, <!WA28><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/pip1_5.gif">page 5</A>, <!WA29><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/pip1_6.gif">page
6</A> 
  </UL>
<LI>Homework 4: <!WA30><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework4.html">Memory Hierarchy</A>
  <UL>
  <LI>Solutions: <!WA31><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/cache1_1.gif">page 1</A>, <!WA32><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/cache1_2.gif">page
2</A>, <!WA33><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/cache1_3.html">page 3</A> 
  </UL>
<LI>Homework 5: <!WA34><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework5.html">More Memory Hierarchy</A>
  <UL>
  <LI>Solutions: <!WA35><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw5_1.gif">page 1</A>, <!WA36><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw5_2.gif">page
2</A>, <!WA37><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw5_3.gif">page 3</A> , <!WA38><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw5_4.gif">page
4</A>
  </UL>
<LI>Homework 6: <!WA39><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework6.html">Input/Output</A> 
  <UL>
  <LI>Solutions: <!WA40><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw6_1.gif">page 1</A>, <!WA41><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw6_2.gif">page
2</A>, <!WA42><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw6_3.gif">page 3</A>, <!WA43><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw6_4.gif">page
4</A>, <!WA44><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/hw6_5.gif">page 5</A>
  </UL>
<LI>Homework 7: <!WA45><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/Homework7.html">Parallel Architectures</A>
  <UL>
  <LI>Solutions: <!WA46><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/solutions/last_micro_hw.gif">page 1</A>
  </UL>
</UL>
<H3>Design Projects: </H3>
<UL>
<LI><!WA47><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/maxfinder.ps">The Maxfinder Processor</A> 
<LI><!WA48><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/datapath.ps">MICA (Minimally Interesting Computer
Architecture) Datapath Design</A> 
<LI><!WA49><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/assignments/processor.ps">MICA Processor Design</A> 
  <UL>
  <LI><!WA50><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/lilia/rom_p1.gif">Using ROMs in Xilinx, p. 1</A> 
  <LI><!WA51><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/lilia/rom_p2.gif">Using ROMs in Xilinx, p. 2</A> 
  <LI><!WA52><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/lilia/rom_p3.gif">Using ROMs in Xilinx, p. 3</A> 
  <LI><!WA53><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/lilia/rom_p4.gif">Using ROMs in Xilinx, p. 4</A> 
  <LI><!WA54><A HREF="http://wizard.cse.nd.edu/class_data/cse322/www/lilia/rom_p5.gif">Using ROMs in Xilinx, p. 5</A> 
  </UL>
</UL>
<H3>Class newsgroup: <!WA55><A HREF="news:nd.courses.cse322">nd.courses.cse322</A>
</H3>
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